The cable-based physical interface uses DC-level line states for
signaling during initialization and arbitration. The backplane
environment uses dominate mode addresses for arbitration and does
not have the initialization requirements of the cable environment because
the topology does not contain repeaters. The physical addresses
may be set by the slot position within the chassis. Due to the
differences, a backplane-to-cable bridge is required to connect
these two environments. Because of the commonality of the link
and other layers, this bridge is quite simple, needing only to
core and reclock the packets.
The signals transmitted on both the cable and backplane environments
are NRZ with Data-Strobe (DS) encoding. DS encoding allows only
one of the two signal lines to change each data bit period, essentially
doubling the jitter tolerance with very little additional circuitry
overhead in the hardware. DS encoding is licensed from SGS-Thomson/INMOS
and is used in other serial interfaces such as P1355
Protocol
Both asynchronous and isochronous data transfers are supported.
The asynchronous format transfers data and transaction layer information
to an explicit address. The isochronous format broadcasts data
based on channel numbers rather than specific addressing. Isochronous
packets are issued on the average of each 125 µ in support of
time-sensitive applications. Providing both asynchronous and isochronous
formats on the same interface allows both non-real-time critical
applications-such as printers, STGTs and scanners-and real-time
critical applications-such as video and audio-to operate on the
same bus.
The tree topology is resolved during a sequence of events triggered
each time a new node is added or removed from the network. This
sequence starts with a bus reset phase, where all previous information
about a topology is cleared. The tree ID sequence determines the
actual tree structure. During the tree ID process, each node is
assigned an address and a root node is dynamically assigned, or
it is possible to force a particular node to become the root.
After the tree is formed, a self-ID phase allows each node on
the network to identify itself to all other nodes. After all of
the information has been gathered on each node, the bus goes into
an idle state waiting for the beginning of the standard arbitration
process.
An additional feature is the ability of transactions at different
speeds to occur on a single device medium (for example, some devices
can communicate at 100 Mbps while others communicate at 200 Mbps
and 400 Mbps). Use of multispeed transactions on a single 1394
serial bus requires consideration of each node's maximum capabilities
when laying out the connections to ensure that the path between
two higher-speed nodes is not blocked by a device with base-rate
abilities.
Conclusion
The 1394-1995 serial-bus has the bandwidth capacity to displace most
other peripheral connection communication methods in use today,
including Centronix parallel, RS232, SCSI and Apple's Desktop
Bus, and consolidate them into a unified high-performance serial
bus. As the technology is developed and deployed, new interfaces
such as direct connect video I/O can find a home where the physical
limitations of today's interconnect prevent wide deployment. The
serial bus' memory space addressing is a perfect fit for "slotless"
systems such as PDAs. Finally, the "hot plugging," power
sourcing and dynamic reconfiguration abilities make 1394 a userfriendly
environment. The features of 1394 will allow plugging in a computer
expansion system as easily as plugging into AC power, providing
communications on demand without having to shutdown and reconfigure
each time an I/O device is added or removed.
TI Solutions for 1394
TI has led the industry with 1394 solutions. In late 1994, TI introduced
the industry's first fully compliant 1394 chipset. The chipset is composed
of two devices: a cable physical layer interface chip, TSB11C01, and the
link layer controller chip, TSB12C01A. The TSB11C01 physical layer chip is
a 5-V, 3-port cable transceiver/arbiter operating at 100 megabits per
second. It includes logic necessary to perform the arbitration and bus
initialization functions. The TSB12C01A link layer chip transmits and
receives correctly formatted 1394 packets and supports isochronous
(real-time) data transfers. It contains an on-board, user-configurable 512
by 4 byte FIFO memory as well as configuration registers. The link layer
device is designed to operate at up to 400 megabits per second. Both
devices support optional isolation recommended in the IEEE 1394-1995
standard.
Figure 3 is a block diagram showing the TSB11C01 and the TSB12C01
implementing a cable-based topology.
Since 1994, TI has added to their 1394 high-speed serial bus product offering
by introducing the TSB12LV22 (OHCI-Lynx),TSB12LV21A (PCILynx), TSB12LV31 (GPLynx), TSB21LV03A, TSB11LV01, and TSB14C01A.
The TSB12LV21A (PCILynx) 1394 to PCI bus link layer controller provides
direct connectivity between the PCI bus and the 1394 high speed serial bus,
5 DMA channels, user-configurable FIFO memory and an 8/16 bit Zoom Video
(ZV)/Auxiliary port. The TSB12LV31 (GPLynx) is a designed as a peripheral link
layer capable of 200Mbps and includes 200byte FIFO with an Isochronous Port and
a 8/16-bit I/F. The TSB21LV03A physical layer chip is a 3.3-V, 3-port
cable transceiver/arbiter operating at 200/100 megabits per second. The
TSB11LV01 physical layer chip is a 3-V, 1-port cable transceiver/arbiter
operating at 100 megabits per second, ideal for peripheral applications.
Figure 4 is a block diagram showing the TSB12LV21A (PCILynx) and the
TSB21LV03A in a typical configuration. The physical layer cable connection
for the 1394 peripheral devices could be the TSB11C01, TSB21LV03A or
TSB11LV01.
The TSB14C01A provides the physical layer functions needed to implement a
single port node in a backplane-based 1394 network. The TSB14C01A is
designed to interface with a link-layer controller such as the TSB12C01A,
and requires a transceiver to interface the backplane environment.
Figure 5 is a block diagram showing the TSB12C01A and TSB14C01A
backplane-based 1394 network.
TI also offers the industry's first broad range of affordably priced 1394
designer kits. These 1394
Designer Kits enable designers of computers, computer
peripherals, telecom and consumer electronics to develop new products that
incorporate the 1394 high-speed serial bus.