1394 High Speed Serial Bus

Link Layer Devices

MPEG2Lynx - TSB12LV41
DVLynx - TSB12LV42
GPLynx - TSB12LV31
GP2Lynx - TSB12LV32
PCILynx2 - TSB12LV21B
PCILynx - TSB12LV21A
OHCI-Lynx - TSB12LV22
TSB12LV01
TSB12C01A

Physical Layer Devices

TSB21LV03A
TSB11C01
TSB11LV01
TSB14C01A
TSB41LV0x
1394 Designer's Kits

1394 Serial Bus Devices

GP2Lynx - TSB12LV32

Product Description

The TSB12LV32 (GP2Lynx) is a high-performance General-Purpuse IEEE 1394.A Link-Layer Controller (LLC) with the capability of transferring data between a host controller, the 1394 phy-link interface, and external devices connected to the local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical layer device and is supported by the LLC. The LLC provides the control for transmitting and receiving 1394 packet data between the micro-controller interface and the phy-link interface via internal 4K byte FIFOs at rates up to 400Mbit/s. The TSB12LV32 transmits and receives correctly formatted 1394 packets, generates and detects the start of isochronous packets, communicates transaction layer transmit requests to the phy, and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV32 is capable of being Cycle Master (CM), Isochronous Resource Manager (IRM), bus manager, and supports reception of isochronous data on two channels.

The TSB12LV32 has support to directly interfaces to most microprocessors/microcontrollers including programmable endian swapping. TSB12LV32 has a generic 16/8-bit host bus interface which supports the ColdFireTM Microcontroller mode at rates up to 60Mhz. The micro-interface may operate in byte or word (16 bit) accesses. The Data Mover block in GP2Lynx is meant to handle an external memory interface of large data blocks. The port can be configured to either transmit or receive data packets. The packets can be either asynchronous, isochronous, or streaming data packets. Asynchronous or Isochronous receive packets will be routed to the DM port or the GRF via the receiver routing control logic.

The internal FIFO is separated into a transmit FIFO and a receive FIFO each of 517 quadlets (2 Kbytes). Asynchronous packets may be transmitted from the DM port or the internal FIFO. If there is contention the FIFO has priority and will be transmitted first.

Target Applications

  • Digital Cameras

  • Printers

  • Scanners

    For more information on the GP2Lynx - TSB12LV32, please contact your local TI sales office.