1394 High Performance Serial Bus

1394 Technical Overview


What is 1394?

1394-1995 is an IEEE designation for a high performance serial bus. This serial bus defines both a backplane (for example, VME, FB+) physical layer and a point-to-point cable-connected virtual bus. The backplane version operates at 12.5, 25 or 50 Mbits/sec, whereas the cable version supports data rates of 100, 200 and 400 Mbits/ sec across the cable medium supported in the current standard. Both versions are totally compatible at the link layer and above. The interface standard defines transmission method, media and protocol.

The primary application of the cable version is the integration of I/O connectivity at the back panel of personal computers using a low-cost, scalable, high-speed serial interface. The 1394 standard also provides new services such as realtime I/O and live connect/disconnect capability for external devices including disk drives, printers and hand-held peripherals such as scanners and cameras

Why was 1394 developed?

The need for 1394 and other next-generation network topologies and protocols is driven by the rapidly growing need for mass information transfer. Typical LANs and WANs simply cannot provide cost-effective connection capabilities nor do they easily support guaranteed bandwidth for "mission critical" applications. Additionally, parallel high-speed communications such as SCSI are not suited to long distances and do not support live connect/disconnect, making reconfiguration time-consuming. Other factors driving next generation protocols such as 1394 include the need for reliability, durability and universal interconnection.

Figure 1 compares the relative performance capabilities of several communication technologies and a timetable of serial and parallel communication solutions. The chart clearly shows that 1394 bandwidth far exceeds many of the communication standards associated with PCs and compares favorably with ATM, HPPI and fiber channels.

Topology

The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory space interconnected between devices, or as if devices resided in slots on the main backplane. Device addressing is 64 bits wide, partitioned as 10 bits for network Ids, 6 bits for node Ids and 48 bits for memory addresses. The result is the capability to address 1023 networks of 63 nodes, each with 281 terabytes of memory. Memory-based addressing, rather than channel addressing, views resources as registers or memory that can be accessed with processor-to-memory transactions. Each bus entity is termed a "node," to be individually addressed, reset and identified. Multiple nodes may physically reside in a single module, and multiple ports may reside in a single node.

Some key features of the 1394 topology are multi-master capabilities, live connect/disconnect (hot plugging) capability. venderless cabling connectors on interconnect cabling and dynamic node address allocation as nodes are added to the serial chain. Another feature is that transmission speed is scalable from approximately 100 Mbps to 400 Mbps.

Each node also acts as a repeater, allowing nodes to be chained together to form a tree topology. Due to the high speed of 1394, the distance between each node or hop should not exceed 4.5m and the maximum number of hops in a chain is 16, for a total maximumend-to-end distance of 72m. Cable distance between each node is limited primarily by signal attenuation. An inexpensive cable with 28-gauge signal pairs can be up to 4.5 meters long. The most widely separated nodes must have 16 or fewer cable hops between them. This gives an end-to-end distance of 72 to 224 meters.

Figure 2 is a block diagram showing a system that uses both the backplane and the cable topologies. The only restriction on the cable topologies is that a maximum of 63 nodes can be connected in a simple no-loops tree with a 00 span of 16 or fewer hops. The cable environment uses a X three-pair shielded cable and a miniature connector to carry transmit/receive data as well as to source or sink power (between 8 and 40 Vdc at no more than 1.5 A). A unique feature of the 1394 cable version is the distribution of power through the cable for operation of the transceiver's repeating functions even if the node power is off.

The cable-based physical interface uses DC-level line states for signaling during initialization and arbitration. The backplane environment uses dominate mode addresses for arbitration and does not have the initialization requirements of the cable environment because the topology does not contain repeaters. The physical addresses may be set by the slot position within the chassis. Due to the differences, a backplane-to-cable bridge is required to connect these two environments. Because of the commonality of the link and other layers, this bridge is quite simple, needing only to core and reclock the packets.

The signals transmitted on both the cable and backplane environments are NRZ with Data-Strobe (DS) encoding. DS encoding allows only one of the two signal lines to change each data bit period, essentially doubling the jitter tolerance with very little additional circuitry overhead in the hardware. DS encoding is licensed from SGS-Thomson/INMOS and is used in other serial interfaces such as P1355

Protocol

Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and transaction layer information to an explicit address. The isochronous format broadcasts data based on channel numbers rather than specific addressing. Isochronous packets are issued on the average of each 125 µ in support of time-sensitive applications. Providing both asynchronous and isochronous formats on the same interface allows both non-real-time critical applications-such as printers, STGTs and scanners-and real-time critical applications-such as video and audio-to operate on the same bus.

The tree topology is resolved during a sequence of events triggered each time a new node is added or removed from the network. This sequence starts with a bus reset phase, where all previous information about a topology is cleared. The tree ID sequence determines the actual tree structure. During the tree ID process, each node is assigned an address and a root node is dynamically assigned, or it is possible to force a particular node to become the root. After the tree is formed, a self-ID phase allows each node on the network to identify itself to all other nodes. After all of the information has been gathered on each node, the bus goes into an idle state waiting for the beginning of the standard arbitration process.

An additional feature is the ability of transactions at different speeds to occur on a single device medium (for example, some devices can communicate at 100 Mbps while others communicate at 200 Mbps and 400 Mbps). Use of multispeed transactions on a single 1394 serial bus requires consideration of each node's maximum capabilities when laying out the connections to ensure that the path between two higher-speed nodes is not blocked by a device with base-rate abilities.

Conclusion

The 1394-1995 serial-bus has the bandwidth capacity to displace most other peripheral connection communication methods in use today, including Centronix parallel, RS232, SCSI and Apple's Desktop Bus, and consolidate them into a unified high-performance serial bus. As the technology is developed and deployed, new interfaces such as direct connect video I/O can find a home where the physical limitations of today's interconnect prevent wide deployment. The serial bus' memory space addressing is a perfect fit for "slotless" systems such as PDAs. Finally, the "hot plugging," power sourcing and dynamic reconfiguration abilities make 1394 a userfriendly environment. The features of 1394 will allow plugging in a computer expansion system as easily as plugging into AC power, providing communications on demand without having to shutdown and reconfigure each time an I/O device is added or removed.

TI Solutions for 1394

TI has led the industry with 1394 solutions. In late 1994, TI introduced the industry's first fully compliant 1394 chipset. The chipset is composed of two devices: a cable physical layer interface chip,
TSB11C01, and the link layer controller chip, TSB12C01A. The TSB11C01 physical layer chip is a 5-V, 3-port cable transceiver/arbiter operating at 100 megabits per second. It includes logic necessary to perform the arbitration and bus initialization functions. The TSB12C01A link layer chip transmits and receives correctly formatted 1394 packets and supports isochronous (real-time) data transfers. It contains an on-board, user-configurable 512 by 4 byte FIFO memory as well as configuration registers. The link layer device is designed to operate at up to 400 megabits per second. Both devices support optional isolation recommended in the IEEE 1394-1995 standard.

Figure 3 is a block diagram showing the TSB11C01 and the TSB12C01 implementing a cable-based topology.

Since 1994, TI has added to their 1394 high-speed serial bus product offering by introducing the TSB12LV22 (OHCI-Lynx),TSB12LV21A (PCILynx), TSB12LV31 (GPLynx), TSB21LV03A, TSB11LV01, and TSB14C01A. The TSB12LV21A (PCILynx) 1394 to PCI bus link layer controller provides direct connectivity between the PCI bus and the 1394 high speed serial bus, 5 DMA channels, user-configurable FIFO memory and an 8/16 bit Zoom Video (ZV)/Auxiliary port. The TSB12LV31 (GPLynx) is a designed as a peripheral link layer capable of 200Mbps and includes 200byte FIFO with an Isochronous Port and a 8/16-bit I/F. The TSB21LV03A physical layer chip is a 3.3-V, 3-port cable transceiver/arbiter operating at 200/100 megabits per second. The TSB11LV01 physical layer chip is a 3-V, 1-port cable transceiver/arbiter operating at 100 megabits per second, ideal for peripheral applications.

Figure 4 is a block diagram showing the TSB12LV21A (PCILynx) and the TSB21LV03A in a typical configuration. The physical layer cable connection for the 1394 peripheral devices could be the TSB11C01, TSB21LV03A or TSB11LV01. The TSB14C01A provides the physical layer functions needed to implement a single port node in a backplane-based 1394 network. The TSB14C01A is designed to interface with a link-layer controller such as the TSB12C01A, and requires a transceiver to interface the backplane environment.

Figure 5 is a block diagram showing the TSB12C01A and TSB14C01A backplane-based 1394 network. TI also offers the industry's first broad range of affordably priced 1394 designer kits. These 1394 Designer Kits enable designers of computers, computer peripherals, telecom and consumer electronics to develop new products that incorporate the 1394 high-speed serial bus.

(c) Copyright 1998 Texas Instruments Incorporated. All rights reserved.
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