1394 High Speed Serial Bus

Link Layer Devices

MPEG2Lynx - TSB12LV41
DVLynx - TSB12LV42
GPLynx - TSB12LV31
GP2Lynx - TSB12LV32
PCILynx2 - TSB12LV21B
PCILynx - TSB12LV21A
OHCI-Lynx - TSB12LV22
TSB12LV01
TSB12C01A

Physical Layer Devices

TSB21LV03A
TSB11C01
TSB11LV01
TSB14C01A
TSB41LV0x
1394 Designer's Kits

1394 Serial Bus Devices

TSB12LV01

Product Description

The TSB12LV01 provides a high-performance IEEE 1394-1995 interface with the capability of transferring data between the 32-bit host controller and external devices connected to the local bus interface. The 1394 phy-link interface provides the connection to the 1394 physical (phy) layer device and is supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394 packet data between the FIFO and phy-link interface at rates of 100Mbit/s, 200Mbit/s, and 400Mbit/s. The TSB12LV01 transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check (CRC). The TSB12LV01 is capable of being cycle master and supports reception of isochronous data on two channels. TSB12LV01 has a generic 32-bit host bus interface, which makes connection to most 32-bit hosts fairly simple. The LLC also provides the capability to receive status from the physical layer device and to access the physical layer control and status registers by the application software.

An internal 2K-byte partitionable FIFO is provided that can be configured as multiple variable-size FIFOs and eliminates the need for external FIFOs. The separate FIFO can be user configured to support general 1394 receive, asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by appropriately sizing the asynchronous transmit FIFO (ATF) and isochronous transmit FIFO (ITF), with the remaining FIFO allocated to the general receive FIFO (GRF).

Features:

  • Cycle Start Packets can be stored in the GRF
  • Isochronous and Asynchronous packet transmit and receive can be enabled/disabled independently. Asynchronous transmit is disabled upon reset, whil isochronous tansmit and receive is unaffected.
  • One, two or all isochronous packets can be received.
  • When receiving packets, RxDta can be programmed to interrupt the host processor on block boundaries, so the host can retrieve data from the GRF when each block is available. This is especially useful if the GRF is smaller than the expected receive packet size. RxDta can also be programmed to interrupt the host processor when each packet is received.
  • Host bus burst mode data transfer is supported, at the peak rate of one quadlet (four bytes) per BClk cycle for ATF write, ITF write, and GRF read.
  • A FIFO status read can be accomplished in three BClk cycles: 1. Address cycle 2. Data cycle 3. Idle cycle
  • Several changes in the register map have been made to improve host bus data throughput and reduce status read and interrupt overhead. ATF Status (30h), ITF Status (34h) and GRF Status (3Ch) contains only status information. FIFO control (1Ch) is defined to control ATF size, ITF size, clear FIFO function and block size for GRF received packet. ATF Status register and ITF status register will report flags: full, empty and available space for host bus burst write. GRF status register will report flags: empty, total stored data count and next received block size.
  • Maximum data throughput on the host bus interface is 132Mbyte/sec if Bclk is run at 33 MHz.

    Target Applications

  • High Speed Peripheral Devices

    The TSB12LV01 provides a way to add 1394 connections to any high speed digital device.