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1394 Serial Bus Devices
TSB12LV01
Product Description
The TSB12LV01 provides a high-performance IEEE 1394-1995 interface with the capability of transferring data
between the 32-bit host controller and external devices connected to the local bus
interface. The 1394 phy-link interface provides the connection to the 1394 physical (phy) layer device and is
supported by the link-layer controller (LLC). The LLC provides the control for transmitting and receiving 1394
packet data between the FIFO and phy-link interface at rates of 100Mbit/s, 200Mbit/s, and 400Mbit/s. The
TSB12LV01 transmits and receives correctly-formatted 1394 packets and generates and inspects the 32-bit
cyclic redundancy check (CRC). The TSB12LV01 is capable of being cycle master and supports reception of
isochronous data on two channels. TSB12LV01 has a generic 32-bit host bus interface, which makes
connection to most 32-bit hosts fairly simple. The LLC also provides the capability to receive status from the
physical layer device and to access the physical layer control and status registers by the application software.
An internal 2K-byte partitionable FIFO is provided that can be configured as multiple variable-size FIFOs and eliminates
the need for external FIFOs. The separate FIFO can be user configured to support general 1394 receive,
asynchronous transmit, and isochronous transmit transfer operations. These functions are accomplished by
appropriately sizing the asynchronous transmit FIFO (ATF) and isochronous
transmit FIFO (ITF), with the remaining FIFO allocated to the general receive FIFO (GRF).
Features:
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