/*
** @(#)8530.h	1.4
**
** Definitions for the Z 8530 Multi-protocol Serial Controller
*/

/*
** Port addresses
*/

#define	SCC_INTREG	0x0306		/* interupt register 		*/

#define CHA_DATA	0x0286		/* channel a addresses, needed  */
#define CHA_CTL		0x0282		/* for cico         		*/

struct mpsc {
	unsigned int cmd;
	unsigned int data;
};

/*
** Register Bit definitions
*/

/*
** Write register 0
*/
#define	R0		0x00		/* select register 0		*/
#define	R1		0x01		/* select register 1		*/
#define	R2		0x02		/* select register 2		*/
#define	R3		0x03		/* select register 3		*/
#define	R4		0x04		/* select register 4		*/
#define	R5		0x05		/* select register 5		*/
#define	R6		0x06		/* select register 6		*/
#define	R7		0x07		/* select register 7		*/
#define R8              0x08            /* select register 8            */
#define R9              0x09            /* select register 9            */
#define R10             0x0A            /* select register 10           */
#define R11             0x0B            /* select register 11           */
#define R12             0x0C            /* select register 12           */
#define R13             0x0D            /* select register 13           */
#define R14             0x0E            /* select register 14           */
#define R15             0x0F            /* select register 15           */

#define RES_EXT         0x10            /* reset ext/status interrupts  */
#define	SND_ABORT	0x18		/* send abort ( SDLC )		*/
#define	INT_NXT_CHR	0x20		/* enable intr on next rcv char	*/
#define	RES_TXINT	0x28		/* reset xmit intr/dma pending	*/
#define	RES_ERR		0x30		/* reset error			*/
#define	RES_IUS		0x38		/* end-of-interrupt		*/
#define	RES_RXCRC	0x40		/* reset rcv CRC checker	*/
#define	RES_TXCRC	0x80		/* reset xmit CRC checker	*/
#define	RES_TXEOM	0xC0		/* reset xmit underrun/eom latch*/

/*
** Write register 1
*/
#define	ENB_EXT		0x01		/* enable ext/status interrupts	*/
#define	ENB_TX_INT	0x02		/* enable xmit intr/dma		*/
#define PAR_SPEC_COND   0x04            /* parity is special condition  */
#define	ENB_1ST_RX	0x08		/* enable intr on 1st rcv char	*/
#define	ENB_ALL_RXP	0x10		/* enable intr on all chars, 	*/
					/*     or special condition	*/
#define	ENB_ALL_RX	0x18		/* enable intr on special 	*/
					/*     condition only           */
#define	WQ_ON_RX	0x20		/* wait/req on receive		*/
#define REQ_ON_WQ	0x40		/* wait/req used as dma request */
#define	ENB_WQ		0x80		/* wait/req enable		*/

/*
** Write register 2 is interrupt vector ( one register for both channels )
*/

/*
** Write register 3
*/
#define	ENB_RX		0x01		/* enable receiver		*/
#define	SYNC_INHB	0x02		/* sync char load inhibit	*/
#define	ADDR_SRCH	0x04		/* addr srch mode ( SDLC )	*/
#define	ENB_RXCRC	0x08		/* enable rcv crc		*/
#define	HUNT_MODE	0x10		/* enter hunt mode		*/
#define	AUTO_ENBL	0x20		/* auto enables			*/
#define	RX_5BIT		0x00		/* rcv 5 bits per char		*/
#define	RX_7BIT		0x40		/* rcv 7 bits per char		*/
#define	RX_6BIT		0x80		/* rcv 6 bits per char		*/
#define	RX_8BIT		0xC0		/* rcv 8 bits per char		*/

/*
** Write register 4
*/
#define	ENB_PARITY	0x01		/* enable parity		*/
#define	EVEN_PAR	0x02		/* even parity			*/
#define	ENB_SYNC	0x00		/* enable sync mode		*/
#define	STOPBIT1	0x04		/* one stop bit			*/
#define	STOPBIT15	0x08		/* one and a half stop bits	*/
#define	STOPBIT2	0x0C		/* two stop bits		*/
#define	SYNC_8BIT	0x00		/* eight bit sync char		*/
#define	SYNC_16BIT	0x10		/* sixteen bit sync char	*/
#define	SDLC_HDLC	0x20		/* sdlc/hdlc mode flag		*/
#define	EXT_SYNC	0x30		/* external sync mode		*/
#define	CLOCKX1		0x00		/* clock times 1		*/
#define	CLOCKX16	0x40		/* clock times 16		*/
#define	CLOCKX32	0x80		/* clock times 32		*/
#define	CLOCKX64	0xC0		/* clock times 64		*/

/*
** Write register 5
*/
#define	ENB_TXCRC	0x01		/* enable xmit crc		*/
#define	RTS		0x02		/* assert RTS			*/
#define	CRC_MODE	0x04		/* sdlc/crc16 crc mode		*/
#define	ENB_TX		0x08		/* enable xmitter		*/
#define	SND_BREAK	0x10		/* send a break			*/
#define	TX_5BIT		0x00		/* xmit 5 bits per char		*/
#define	TX_7BIT		0x20		/* xmit 7 bits per char		*/
#define	TX_6BIT		0x40		/* xmit 6 bits per char		*/
#define	TX_8BIT		0x60		/* xmit 8 bits per char		*/
#define	DTR		0x80		/* assert DTR			*/

/*
** Write register 6 contains the transmit sync char in sync mode
*/

/*
** Write register 7 contains the receive sync char in sync mode
*/

/*
** Write register 8 is the transmit data register
*/

/*
** Write register 9 ( one register for both channels )
*/
#define DIS_M_INT       0x00            /* disable master intrrupt      */
#define STAT_AFF_VECT   0x01            /* vector includes status       */ 
#define NO_VECT         0x02            /* no vector                    */
#define DIS_L_CHAIN     0x04            /* disable lower chain          */
#define ENB_M_INT       0x08            /* enable master interrupt      */
#define STAT_H_L        0x10            /* status high, status low      */
#define RES_CHAN_A      0x40            /* reset channel a              */
#define RES_CHAN_B      0x80            /* reset channel b              */
#define HARD_RESET      0xC0            /* force hardware reset         */

/*
** Write register 10
*/

/*
** Write register 11
*/
#define BR_GEN_OUTP     0x02            /* br generator output          */
#define TRXC_O_I        0x04            /* direction of trxc            */
#define TX_CLOCK        0x10            /* transmit clock               */
#define RX_CLOCK        0x40            /* receive clock                */

/*
** Write register 12
*/
/* br time constant low byte    */

/*
** Write register 13
*/
/* br time constant high byte   */

/*
** Write register 14
*/
#define BR_ENB          0x01            /* br generator enable          */
#define BR_SRC_PCLK	0x02            /* br generator enable          */
#define TX_REQUEST	0x04		/* use DTR/REQ pin as dma request */
#define AUTO_ECHO	0x08		/* auto echo */
#define LOCLOOP		0x10		/* local loopback		*/

/*
** Write register 15
*/

#define	ZERO_COUNT_IE	0x02		/* zero count interrupt enable	*/
#define	DCD_IE		0x08		/* dcd interrupt enable		*/
#define	SYNCHUNT_IE	0x10		/* sync/hunt interrupt enable	*/
#define	CTS_IE		0x20		/* cts interrupt enable		*/
#define UNDERRUN_IE	0x40		/* tx underrun/eom interrupt e. */
#define BREAK_IE	0x80		/* break-abort interrupt enable */

/*
** Read register 0
*/
#define	RX_CHAR_AVAIL	0x01		/* rcv character is available	*/
#define	ZERO_COUNT	0x02		/* zero count           	*/
#define	TX_BUFMT	0x04		/* xmit buffer empty		*/
#define	DCD		0x08		/* carrier detect is present	*/
#define	SYNCHUNT	0x10		/* sync/hunt			*/
#define	CTS		0x20		/* clear-to-send is present	*/
#define	TX_UNDERRUN	0x40		/* xmit underrun/eom		*/
#define	BREAK		0x80		/* break/abort detected		*/

/*
** Read register 1
** NOTE: The definitions for residue data are not defined because
**	 of lack of interest
*/
#define	PARITY_ERR	0x10		/* parity error			*/
#define	RX_OVERRUN	0x20		/* rcv overrun			*/
#define	FRAME_ERR	0x40		/* framing/crc error		*/
#define	END_OF_FRAME	0x80		/* end-of-frame ( SDLC )	*/
#define ALL_SENT	0x01		/* all send in async mode	*/

/*
** Read register 2 ( Channel B ) is the interrupt vector,
** including status information.
*/
#define	INTR_TYPE	0x0E		/* bits that are modified	*/
#define	CHANA_INT	0x08		/* values >= this are from Chn A*/
#define	TX_INT		0x00		/* xmit buffer empty		*/
#define	EXTCHNG		0x02		/* ext/status change		*/
#define	RCVCHAR		0x04		/* rcv char available		*/
#define	SPECRCV		0x06		/* special receive condition	*/

/*
** Read register 3 is the interrupt pending register ( only channel a )
*/
#define CHB_EXTSTA_INT  0x01            /* channel b ext stat intr      */
#define CHB_TX_INTR     0x02            /* channel b tx buffer empty    */
#define CHB_RX_INTR     0x04            /* channel b rx char avail      */
#define CHA_EXTSTA_INT  0x08            /* channel a ext stat intr      */
#define CHA_TX_INTR     0x10            /* channel a tx buffer empty    */
#define CHA_RX_INTR     0x20            /* channel a rx char avail      */

/*
** Read register 8 is the receive data register
*/

/*
** Read register 10
*/

#define	ONLOOP		0x02		/* on loop			*/
#define	LOOPSEND	0x10		/* loop sending			*/
#define	TWO_C_MISS	0x40		/* two clocks missing		*/
#define	ONE_C_MISS	0x80		/* one clock missing		*/

/*
** Read register 12
*/

/*
** Read register 13
*/

/*
** Read register 15
*/
