/*      Copyright (c) 1985 AT&T */
/*        All Rights Reserved   */

/*      THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF AT&T     */
/*      The copyright notice above does not evidence any        */
/*      actual or intended publication of such source code.     */

/* @(#)8259.h	1.8 */
/*
** constants and definitions for the
** 8259 Programmable Interrupt Controller (PIC)
*/

/*
** bit definitions for Initialization Command Words 1 and 2
*/
#define	NEED_ICW4	0x01		/* ICW4 is needed		*/
#define	SNGL		0x02		/* single mode (reset = cascade)*/
#define	ADI		0x04		/* address interval		*/
#define	LTIM		0x08		/* level triggered mode		*/
#define	ALWAYS_SET	0x10		/* this bit is always set	*/

/*
** bit definitions for Initialization Command Word 3
*/
#define	MSLAVE_HERE	0x80		/* master connect to slave here	*/
#define	SSLAVE_HERE	0x07		/* slave connect to master here	*/

/*
** bit definitions for Initialization Command Word 4
*/
#define	MODE_8086	0x01		/* 8086 mode of operation	*/
#define	AUTOEOI		0x02		/* automatically generated eoi	*/
#define	MASTER		0x04		/* PIC is master		*/
#define	BUFFERED	0x08		/* buffered mode enabled	*/
#define	SFNM		0x10		/* special fully nested mode	*/

/*
** bit definitions for Operational Command Word 2
*/
#define	EOI		0x20		/* end-of-interrupt		*/
#define	SPECIFIC_EOI	0x40		/* enables specific eoi mode	*/
#define	ROTATE		0x80		/* rotate on eoi		*/

/*
** base locations for the PICs to interrupt at
*/
#define	MBASE		0x20		/* 0x20 to 0x27			*/

/*
** combinatorial bit defines for initialization of the PICs
*/

#define	MICW1		ALWAYS_SET | NEED_ICW4 | ADI | SNGL
#define	MICW2		MBASE
#define	MICW4		MODE_8086

/*
** port addresses
*/
#define	PICSTAT		0x0240		/* address of master PIC status port */
#define	PICLEVEL	0x0242		/* address of master PIC level port  */

/*
** bit definitions for master interrupt masks
*/
#define	ML0		0x01		/* parity error    	*/
#define	ML1		0x02		/* clock               	*/
#define	ML2		0x04		/* sio 8530 		*/
#define	ML3		0x08		/* wini			*/
#define	ML4		0x10		/* network board	*/
#define	ML5		0x20		/* floppy		*/
#define	ML6		0x40		/* qic02		*/
#define	ML7		0x80		/* adma			*/

/*
** composite masks to send to the PIC
** NOTE: Bit set disables the interrupt,
**	 Bit clear enables the interrupt.
*/					/* disable:		*/
#define	SPL0	0  			/*  nothing		*/
#define	SPL5	SPL0 | ML2 | ML7 | ML4  /*  sio	8530, net	*/
#define	SPL6	SPL5 | ML3 | ML5 | ML6	/*  floppy, disk, tape  */
#define	SPL7	SPL6 | ML1		/*  all			*/

/* parity always open */ 

